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Beyond5 (SOI Teknolojileri) ECSEL Projesi
BEYOND5, Building the fully European supply chain on RFSOI, enabling New RF Domains for sensing, Communication, 5G and beyond.
BEYOND5's main goal is to build a European supply chain on Radio Frequency SOI technology and create new RF use cases for sensing, communication, 5G radio and beyond. BEYOND5 is a technology project that aims to produce highly innovative components in Europe (using three pilot lines in two European countries), build the value chain to demonstrate added value at the user level in six different areas, and strengthen the design ecosystem in Europe.
The main aim at BEYOND5 is to develop the three main SOI silicon technologies (ST-RFSOI65, ST-FDSOI28, GF-FDSOI22) and to demonstrate that these technologies can be used in select areas. In order to demonstrate the benefits of SOI technologies, six different demonstrations with real application models close to operational radio systems are targeted. These 6 demonstrations are structured around four main application areas: IoT, V2X, 5G and Sensors.
TÜBİTAK BİLGEM will identify and design receiver path sub-blocks including ADC, PLL, mixer, LNA, filters, digital predistortion and source modulator. Sub-blocks will be fabricated and verified with 65 nm RF-SOI.
MEEP - The MareNostrum Experimental Exascale Platform
The MEEP project explores hardware/software co-designs for exascale supercomputers based on European IP. BSC coordinates the MEEP RIA project, with UNIZG-FER and TÜBİTAK BILGEM as partners.
The aim of the Research and Innovation Action (RIA) consists of activities aiming to establish new knowledge and/or to explore the feasibility of a new or improved processor technology and related for HPC and embedded computing.
The consortium, led by the Barcelona Supercomputing Center (BSC), was granted funding from the European Programme Research and Innovation Action (RIA) to execute the MEEP project, whose resulting technologies aim to create European chips from the further development of follow-on project(s).
The MareNostrum Experimental Exascale Platform (MEEP) project supports the goal of the European Union (EU) program EuroHPC to create competitive European technology integrated into future exascale supercomputers. Specifically, it aims to develop an exploratory supercomputing infrastructure for the development, integration, testing and co-design of a wide range of European technologies, which could form part of future European exascale systems, based on European-developed intellectual property (IP). The ultimate goal is to create an open full-stack (software and hardware) ecosystem that could form the foundation for many other European systems, both in HPC and embedded computing, with benefits for numerous stakeholders within academia and industry.
In order to reach its goals, MEEP brings together three EU partners: BSC (Spain), as coordinator will provide software and hardware as well as expertise to create infrastructure for European chip developing targeting exascale machines, UNIZG-FER (Croatia) will contribute with its significant expertise in architecture and building and deploying FPGA-based systems and TÜBİTAK BILGEM (Turkey) will contribute their deep expertise in verification, architecture and advanced logic design.
According to Peter Hsu, MEEP director at BSC “it is important for us to be the coordinators of such highly competitive technology that will build, create and deploy key technologies of BSC that can reach the market and directly contribute to the evolution of society.” John Davis, MEEP coordinator at BSC, adds “The MareNostrum Experimental Exascale Platform (MEEP), as a performance evaluation at BSC and software development vehicle for future chip designs, will provide European technology that will set a foundation for many systems, both in HPC and beyond.”
The Research and Innovation Action (RIA) programme is part of the European High-Performance Computing Joint Undertaking (EuroHPC JU), which is a public-private partnership in High Performance Computing (HPC), enabling the pooling of European Union (EU) -level resources with the resources of participating EU Member States and participating associated states of the Horizon 2020 programme, as well as private stakeholders. The Joint Undertaking has the twin stated aims of developing a Pan-European supercomputing infrastructure, and supporting research and innovation activities.
The programme develops activities that aim to establish new knowledge and/or to explore the feasibility of a new or improved processor technology, and related products, processes, services and/or solutions for high-performance computing (HPC) and embedded computing. For this purpose, they may include basic and applied research, technology development and integration, testing and validation on a small-scale prototype in a laboratory or simulated environment.
This project has received funding from the European High-Performance Computing Joint Undertaking Joint Undertaking (JU) under grant agreement No 946002. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Spain, Croatia, Turkey.
In MEEP project, TUTEL is responsible for the development and integration of systolic array based neural network inference accelerator (SA-NN). TUTEL works on the RTL implementation of the SA-NN functional core and the integration of the SA-NN module to the Micro Engine unit of the MEEP system. TUBITAK is also working on the OVI (Open Vector Interface) integration and verification, along with preparation of a Python code for GUI debug and RTL result check.
Reference Link: https://www.bsc.es/news/bsc-news/new-processor-emulation-platform-bsc-will-explore-hardwaresoftware-co-designs-exascale
The European Pilot (Pilot Using Independent Local & Open Technologies)
In this project, an accelerator will be developed under the leadership of the Barcelona Computing Center and by a multi-partner international consortium in which we also participate as TUTEL. Accelerators provide the majority of performance in modern High Performance Computing (HPC) systems and are the fundamental building blocks for Exascale systems. The European PILOT (Pilot using Independent Local & Open Technology) will be the first demonstration of two ALL European HPC and High Performance Data Analytics (HPDA) (AI, ML, DL) accelerators, designed, implemented, manufactured, and owned by Europe. The European PILOT combines open source software (SW) and open and proprietary hardware (HW) to deliver the first completely European full stack software, accelerator, and integrated ecosystem based on RISC-V accelerators coupled to any general purpose processor (CPU) via PCIe Gen 6.0 or CXL 3.0. This pilot will demonstrate key HPC and HPDA workloads and software stacks. The European PILOT is also the first to demonstrate an ALL European HPC ecosystem.
The accelerators will be manufactured in the new European GlobalFoundries 12 nm advanced silicon technology, a major demonstration of European technology independence. The European PILOT combines cutting edge research utilizing SW/HW co-design to demonstrate HPC and HPDA accelerators running key applications and libraries in a full software stack including middleware, runtimes, compilers, and tools for the emerging RISC-V ecosystem. The European PILOT is able to produce a full stack (SW and HW) research prototype by leveraging and extending the work done in multiple European projects like: EPI, MEEP, POP2 CoE, EuroEXA, and ExaNeSt. This pre-production system can only be realized with a combination of existing IP, HW emulation using FPGAs, and real ASIC prototypes that demonstrate the full stack feasibility of the hardware and software. Finally, while the applications we use span AI to HPC, the aggressive ASIC implementation (chiplet size and small geometry) will be the smallest technology node manufactured in Europe and can easily be adapted for a near-future HPC implementation.
Figure 1. The European PILOT full stack: 3 HPC and HPDA application domains, down to the Vector (VEC) and ML and Stencil (MLS) European accelerators integrated into open source chassis and racks, agnostic to the host server. The vertical red and green boxes in Stream 2 indicate the application domain and related software and target hardware accelerator, with some components spanning both domains.
Figure 1 shows the main parts of the European Pilot project. In this project, TUTEL takes part in some work packages such as the development of MLS and VEC chips shown in Figure 1, the solution of molecular dynamics systems on the general system, the publication of the project results and the exploitation of the project results. These work packages are given in detail in the proposal document and our roles in this project as TÜTEL are summarized below:
1) Development of HPC and AI (Artificial Intelligence) applications for the solution of molecular dynamics equations on the accelerator system and the emulator of the system which will be developed throughout the project.
2) Bandgap IP, temperature and voltage sensor required for the accelerator system to be developed in the project, and the design of the digital block that controls this sensor, using Global Foundries (GF) 12nm technology and its integration into the system.
3) Design of test chip controller that will test PHY and the IP modules to be used in MLS and VEC chips
4) Development of HPC and AI (Artificial Intelligence) applications for the solution of molecular dynamics equations on the accelerator system and the emulator of the system which will be developed throughout the project.
Reference Link: https://eupilot.eu/
